Analog-to-digital conversion is a process that is often used in electronic devices to implement processing algorithms in the digital domain. As a result, the processing algorithms can be implemented in a much simpler manner, and with reduced chip size and reduced power consumption. There are a variety of different types of analog-to-digital converters (ADCs) in the market today, such as flash ADCs, switched-capacitor ADCs, and pipelined ADCs. Pipelined ADCs have become more prevalent as the demand for faster operation of electronic devices has increased. Specifically, pipelined ADCs can be implemented to quickly and efficiently convert analog input signals to high-resolution digital signals, such that the resolution of a pipelined ADC can be significantly greater than other types of ADCs without sacrificing speed of operation.
FIG. 1 illustrates an example of a typical pipelined ADC 10. The pipelined ADC 10 includes a plurality of pipeline stages 12, numbered 1 through N, where N is a positive integer. The first stage receives an analog input signal AN_IN as an input for which the pipelined ADC 10 is configured to provide a digital output signal DIG_OUT. The pipelined ADC 10 can be implemented in any of a variety of electronic devices, such as computers, portable electronic devices, and/or wireless communication devices.
Each of the pipeline stages 12 of the pipelined ADC 10 is configured to provide a specific portion of the digital output signal DIG_OUT. In the example of FIG. 1, the first pipeline stage 12, labeled STAGE 1, receives the analog input signal AN_IN and provides a most-significant bit portion of the digital output signal DIG_OUT, labeled DIG_OUTMSB. The digital portion DIG_OUTMSB can include one or more of the most-significant bits of the digital signal DIG_OUT. The first pipeline stage 12 also outputs a residue voltage that is a sampled and held voltage of the analog input signal AN_IN.
The residue voltage is provided to a next pipeline stage 12 (not shown) which could provide the next most-significant bits of the digital output signal DIG_OUT based on the residue voltage provided from the preceding stage STAGE 1. Thus, similar to the first pipeline stage STAGE 1, the next pipeline stage provides a residue voltage to the next consecutive stage, and so forth, up to the last pipeline stage 12, demonstrated as STAGE N in the example of FIG. 1. The last stage STAGE N receives a residue voltage from a next-to-last stage, STAGE N−1, and generates the least-significant bit portion of the digital output signal DIG_OUT, demonstrated as DIG_OUTLSB in the example of FIG. 1. The digital portion DIG_OUTLSB can include one or more of the least-significant bits of the digital signal DIG_OUT. Therefore, the digital output signal DIG_OUT, in its entirety, includes each of the digital portions DIG_OUTMSB, DIG_OUTLSB, and all digital portions in between. As a result, a high digital resolution can be achieved for a given sample of the analog input signal AN_IN that is converted to the digital domain.
Upon generating a respective digital portion DIG_OUTX of the digital output signal DIG_OUT, where X is a positive integer that denotes a number corresponding to the specific stage, each of the pipeline stages 12 is configured to generate a residue portion of the analog input signal AN_IN and transfer the residue portion to the next stage. Therefore, each of the pipeline stages 12 includes a closed-loop residue amplifier 14. The closed-loop residue amplifier 14 in the first pipeline stage STAGE 1 is configured to receive the sampled-and-held analog input signal AN_IN and to generate a residue voltage that corresponds to the residue of the most-significant digital portion DIG_OUTMSB. The remaining pipeline stages 12 are each configured to sample-and-hold the residue voltage provided from the preceding pipeline stage 12 and to generate a residue voltage that corresponds to the residue of the digital portion of the respective pipeline stage 12 via the respective closed-loop residue amplifier 14. Thus, the residue voltage VRES—X corresponds to the residue provided to the respective pipeline stage 12 minus the digital portion DIG_OUTX of the respective pipeline stage 12.
FIG. 2 illustrates an example of a pipeline stage 12 of the pipelined ADC 10 of the example of FIG. 1. The pipeline stage 12 in the example of FIG. 2 will be referred to as STAGE X in the discussion herein, such that STAGE X can refer to any of the pipeline stages 12 in the example of FIG. 1. STAGE X includes a sample-and-hold portion 13 and the closed-loop residue amplifier 14. The sample-and-hold portion 13 receives a residue voltage VRES—X−1 from the previous pipeline stage (denoted as X−1 since FIG. 2 demonstrates STAGE X). The residue voltage VRES—X−1 is provided to a sample-and-hold circuit 16, which samples and holds the residue voltage VRES—X−1 to generate a sample-and-hold voltage VSH for STAGE X. The sample-and-hold voltage VSH is provided to a current buffer 18 to generate a voltage VADC, which is output from the current buffer 18 to a local ADC 20. As an example, the local ADC 20 can be a flash ADC. The voltage VADC can be substantially equal to the sample-and-hold voltage VSH, such that the voltage VADC can have an associated current that is sufficient to drive a large capacitive load associated with the local ADC 20. The local ADC 20 thus converts the voltage VADC to a digital portion DIG_OUTX of the digital output signal DIG_OUT. The digital portion DIG_OUTX is also provided to a local digital-to-analog converter (DAC) 22 configured to convert the digital portion DIG_OUTX back to an analog form.
The closed-loop residue amplifier 14 includes an operational amplifier (OP-AMP) 24 that is arranged in a closed-loop, feedback configuration. Specifically, the OP-AMP 24 has an inverting input that is grounded, and an output that is fed back through a feedback resistor RFB to a summation node 26 at a non-inverting input of the OP-AMP 24. The sample-and-hold voltage VSH is also provided to the summation node 26 through a resistor RSH, and a current IDAC flows from the summation node 26 to the DAC 22. The current IDAC can represent a quantization level of the digital portion DIG_OUTX. Therefore, the summation node 26 is a node from which the quantization level of the digital portion DIG_OUTX is subtracted from the sample-and-hold voltage VSH across the residue resistor RSH.
Because the OP-AMP 24 is arranged in a closed-loop, feedback configuration, the output of the OP-AMP 24 is amplified to generate a highly linear output. Specifically, the linearity in the closed-loop configuration of the OP-AMP 24 is achieved based on the substantially high linearity of the passive resistors RFB and RSH, particularly in the resistor RFB being enclosed in the feedback loop of the OP-AMP 24. The highly linear output is thus provided as a residue voltage VRES—X that corresponds to the residue of the voltage provided to the pipeline stage STAGE X (i.e., the residue voltage VRES—S−1 from the previous pipeline stage) minus the quantization level of the digital portion DIG_OUTX. The residue voltage VRES—X is output from STAGE X to the next pipeline stage 12 of the pipelined ADC 10, unless STAGE X is the last pipeline stage 12 in the pipelined ADC 10 (i.e., X=N).
In the examples of FIGS. 1 and 2, each of the signals (e.g., residue voltages) and each of the components are demonstrated as single-ended. However, it is to be understood that each of the signals and components in the examples of FIGS. 1 and 2 can be implemented as differential, such that a given residue voltage VRES can be either a positive portion VRES+ or a negative portion VRES− of a fully differential residue voltage.
As described above, pipelined ADCs can be implemented to provide high resolution digital representations of analog signals very quickly, thus making them very desirable in a variety of electronic device applications. However, because each of the stages amplifies the residue voltage that is provided from the preceding stage in a highly linear manner, and because each of the residue voltages that is sampled and held at each stage is current buffered before being provided to the local ADC, a given pipelined ADC can consume a substantial amount of power. In addition, the OP-AMP components of the closed-loop residue amplifiers can be physically large, such that they can occupy substantial space in an integrated circuit (IC). Such power consumption and size are directly adverse to the goal of reducing power and accommodating the consumer demand for a continuous reduction in size of electronic portable devices. In addition, these devices are typically battery powered, and it is desirable to utilize as little power as possible to operate these devices so that the battery life can be extended. As such, pipelined ADCs typically operate under the trade-off constraints of speed and high resolution at the cost of substantial power consumption and size.